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BGSA141MN10 b g s a 1 41 m n 1 0 lo w r e s i s ta n ce a n t e n n a a p e r t u r e s w i t c h features designed for high-linearity antenna aperture switching and rf tuning applications multiple selectable switch configurations: sp4t/sp3t/spdt/spst ultra low r on resistance of 1.0
at each port in on state low c off capacitance of 270 ff at each port in off state high max rf voltage off state handling low harmonic generation mipi rffe control interface hardware pin swapping function to select 2 usid addresses supply voltage range: 2.3 to 3.6 v no rf parameter change within supply voltage range small form factor 1.1 mm x 1.5 mm rohs and weee compliant package 1.1 x 1.5 mm 2 application impedance tuning antenna tuning inductance tuning tunable filters product validation qualified for industrial applications according to the relevant tests of jedec47/20/22 block diagram final data sheet www.infineon.com revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch table of contents table of contents table of contents 1 1 features 2 2 maximum ratings 3 3 dc characteristics 5 4 rf small signal parameters 6 5 rf large signal parameters 9 6 mipi rffe specification 11 7 application information 17 8 package information 18 final data sheet 1 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch features 1 features designed for high-linearity antenna aperture switching and rf tuning applications multiple selectable switch configurations: sp4t/sp3t/spdt/spst ultra low r on resistance of 1.0
at each port in on state low c off capacitance of 270 ff at each port in off state high max rf voltage off state handling low harmonic generation mipi rffe control interface hardware pin swapping function to select 2 usid addresses supply voltage range: 2.3 to 3.6 v no rf parameter change within supply voltage range small form factor 1.1 mm x 1.5 mm rohs and weee compliant package description the BGSA141MN10 is a versatile single-pole quad throw (sp4t) / single pole triple throw (sp3t) / single pole double throw (spdt) and single pole single throw (spst) rf antenna aperture switch optimized for low c o? as well as low r on enabling applications up to 4.0 ghz. including a rffe digital control interface, this switch oers the possibility to adopt a sp4t, sp3t, spdt along with spst topology for a better flexibility in rf front-end designs. the BGSA141MN10 includes 4 ultra-low r on ports making it ideal for antenna aperture switching and switchable capacitors of high values. this single supply chip integrates on-chip cmos logic driven by a simple, single-pin cmos or ttl compatible control input signal. unlike gaas technology, the 0.1 db compression point exceeds the switch maximum input power level, resulting in linear performance at all signal levels and external dc blocking capacitors at the rf ports are only required if dc voltage is applied externally. due to its very high rf voltage ruggedness, it is suited for switching any reactive devices such as inductors and capacitors in rf matching circuits without significant losses in quality factors. BGSA141MN10 empower its users with a smart usid selection feature. default usid is 0b1100 when data signal is routed to pin 5 and clock signal to pin 6. default usid is 0b1101 when data signal is routed to pin 6 and clock signal to pin 5. this infineon patented feature allows to drive 2 identical BGSA141MN10 parts with the same mipi rffe bus opening higher degree of flexibility and freedom in the pcb design. product name marking package BGSA141MN10 m5 tsnp-10-3 final data sheet 2 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch maximum ratings 2 maximum ratings figure 1: rf operating voltage measurement configuration table 1: maximum ratings, table i at t a = 25 c , unless otherwise specified parameter symbol values unit note / test condition min. typ. max. frequency range f 0.1 C C ghz 1) supply voltage 2) v dd -0.5 C 6 v only for infrequent and short duration time periods storage temperature range t stg -55 C 150 c C rf input power p rf _ max C C 39 dbm pulsed rf input duty cycle of 25 % and 4620 s in on-state, measured per 3gpp ts 45.005 rf voltage v rf _ max C C 44 v short term peaks (1 s in 0.1% duty cycle), exceeding typical linearity, ron and co param- eters, in isolation mode, test condition schematic in fig. 1 esd capability, cdm 3) v esd cdm -1 C +1 kv esd capability, hbm 4) v esd hbm C C class1b - esd capability, system level (rfc port) 5) v esd ant -8 C +8 kv rfc vs system gnd, with 27 nh shunt inductor junction temperature t j C C 125 c C 1) switch has a lowpass response. for higher frequencies, losses have to be considered for their impact on thermal heating. the dc voltage at rf ports v rfdc has to be 0v. 2) note: consider potential ripple voltages on top of v dd . including rf ripple, v dd must not exceed the maximum ratings: v dd = v dc + v ripple . 3) field-induced charged-device model jesd22-c101. simulates charging/discharging events that occur in production equipment and processes. potential for cdm esd events occurs whenever there is metal-to-metal contact in manufacturing. 4) human body model ansi/esda/jedec js-001 ( r = 1,5 k
, c = 100 pf ). 5) iec 61000-4-2 ( r = 330
, c = 150 pf ), contact discharge. final data sheet 3 revision 2.0 2017-06-12 4 4
BGSA141MN10 low resistance antenna aperture switch maximum ratings table 2: maximum ratings, table ii at t a = 25 c , unless otherwise specified parameter symbol values unit note / test condition min. typ. max. maximum dc-voltage on rf-ports and rf-ground v rfdc 0 C 0 v no dc voltages allowed on rf- ports rffe supply voltage v io -0.5 C 3.6 v C rffe control voltage levels v sclk , v sdata -0.7 C v io +0.7 (max. 3.6) v C warning: stresses above the max. values listed here may cause permanent damage to the device. maximum rat- ings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. exposure to conditions at or below absolute maximum rating but above the specified maximum operation conditions may aect device reliability and life time. functionality of the device might not be given under these conditions. final data sheet 4 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch dc characteristics 3 dc characteristics table 3: dc characteristics at t a = ? 40 c to 85 c parameter symbol values unit note / test condition min. typ. max. supply voltage v dd 2.3 2.8 3.6 v C supply current i dd C 80 150 a normal mode C 0.1 2 a low power or default mode rffe supply voltage v io 1.65 1.8 1.95 v C rffe input high voltage 1 v ih 0.7*v io C v io v C rffe input low voltage 1 v il 0 C 0.3*v io v C rffe output high voltage 1 v oh 0.8*v io C v io v C rffe output low voltage 1 v ol 0 C 0.2*v io v C rffe control input capacitance c ctrl C C 2 pf C rffe supply current i vio C 15 25 a idle state 1 sclk and sdata final data sheet 5 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch rf small signal parameters 4 rf small signal parameters table 4: parametric specifications using sp4t configuration parameter symbol values unit state / notes min. typ. max. frequency range f 0.1 4.0 ghz v dd = 2.3 3.6 v , t a = 40 c ... + 85 c , z 0 = 50
rf1, rf2, rf3 or rf4 to rfc on resistance r on sp 4 t C 1.0
rf1, rf2, rf3 or rf4 to rfc off capacitance c off sp 4 t C 270 ff table 5: parametric specifications using sp3t configuration parameter symbol values unit state / notes min. typ. max. frequency range f 0.1 4.0 ghz v dd = 2.3 3.6 v , t a = 40 c ... + 85 c , z 0 = 50
rf1||rf2 or rf3||rf4 to rfc 1) on resistance r on sp 3 t (1) C 0.5
rf1||rf2 or rf3||rf4 to rfc 1) off capacitance c off sp 3 t (1) C 540 ff rf1, rf2, rf3 or rf4 to rfc on resistance r on sp 3 t (2) C 1.0
rf1, rf2, rf3 or rf4 to rfc off capacitance c off sp 3 t (2) C 270 ff 1) rf1 and rf2 or rf3 and rf4 connected together on pcb table 6: parametric specifications using spdt configuration parameter symbol values unit state / notes min. typ. max. frequency range f 0.1 4.0 ghz v dd = 2.3 3.6 v , t a = 40 c ... + 85 c , z 0 = 50
rf1||rf2 and rf3||rf4 to rfc 1) on resistance r on spdt C 0.5
rf1||rf2 and rf3||rf4 to rfc 1) off capacitance c off spdt C 540 ff 1) rf1 and rf2, rf3 and rf4 connected together on pcb final data sheet 6 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch rf small signal parameters table 7: parametric specifications using spst configuration parameter symbol values unit state / notes min. typ. max. frequency range f 0.1 4.0 ghz v dd = 2.3 3.6 v , t a = 40 c ... + 85 c , z 0 = 50
rf1||rf2||rf3||rf4 to rfc 1) on resistance r on spst C 0.25
rf1||rf2||rf3||rf4 to rfc 1) off capacitance c off spst C 1.08 pf 1) rf1, rf2, rf3, rf4 connected together on pcb table 8: rf electrical parameters insertion loss: rf1 to rfc, rf2 to rfc, rf3 to rfc or rf4 to rfc (sp4t mode) (1,2) parameter symbol values unit state / notes min. typ. max. 698 - 960 mhz il sp 4 t 0.1 0.25 0.4 db v dd = 2.3 3.6 v , z 0 = 50
, t a = 40 c ... + 85 c 1710 - 1980 mhz 0.35 0.55 0.7 db 1981 - 2169 mhz 0.45 0.65 1.0 db 2170 - 2690 mhz 0.5 0.80 1.2 db return loss: rf1, rf2, rf3 or rf4 (1,2,3) 698 - 960 mhz rl sp 4 t 16 21 C db v dd = 2.3 3.6 v , z 0 = 50
, t a = 40 c ... + 85 c 1710 - 2690 mhz 12 14 C db isolation: rf1 to rfc, rf2 to rfc, rf3 to rfc or rf4 to rfc (sp4t mode) (1,2,3) 698 - 960 mhz iso sp 4 t 21 25 C db v dd = 2.3 3.6 v , z 0 = 50
, t a = 40 c ... + 85 c 1710 - 1980 mhz 15 18 C db 1981 - 2169 mhz 14 17 C db 2170 - 2690 mhz 13 16 C db isolation: rfc to rfx (isolation mode) (1,2,3) 698 - 960 mhz iso on 17 20 C db v dd = 2.3 3.6 v , z 0 = 50
, t a = 40 c ... + 85 c 1710 - 1980 mhz 12 14 C db 1981 - 2169 mhz 11 13 C db 2170 - 2690 mhz 10 13 C db switching time mipi to rf time t int 0.5 5 6 s 50 % last sclk falling edge to 90 % rf value settled, fig. 2 power up settling time t pus C 10 25 s aer power down mode, fig. 3 1) valid for all rf power levels, no compression behavior 2) on application board without any matching components final data sheet 7 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch rf small signal parameters figure 2: mipi to rf time figure 3: power-up settling time definition power-up settling time definition: a) when the device is already in active mode. b) when changing from low power mode to active mode. aer power-up of vio the device is set to low power mode. an additional mipi instruction is necessary to set the switch to active mode. this case is covered by b) . final data sheet 8 revision 2.0 2017-06-12 90% sclk rf signal sd a t a t int sclk sd a t a t pup vio vb a t b) sclk sd a t a t pup vio vb a t a)
BGSA141MN10 low resistance antenna aperture switch rf large signal parameters 5 rf large signal parameters table 9: rf large signal specifications parameter symbol values unit note / test condition min. typ. max. rf operating voltage v rf _ peak C C 36 v in isolation mode. test condi- tions schematic in fig. 1 harmonic generation up to 12.75 ghz (1,2,3) all rf ports second order harmonics p h 2 C -105 C dbc 25 dbm, f 0 = 786 mhz all rf ports third order harmonics p h 3 C -115 C dbc 25 dbm, f 0 = 786 mhz all rf ports second order harmonics p h 2 C -93 C dbc 33 dbm, f 0 = 824 mhz all rf ports third order harmonics p h 3 C -94 C dbc 33 dbm, f 0 = 824 mhz all rf ports higher order harmonics p hx , x > 3 C C -105 dbc 25 dbm intermodulation distortion imd2 (1,2,3) iip2, low iip2,l C 110 C dbm iip2 conditions, tab. 10 iip2, high iip2,h C 120 C dbm intermodulation distortion imd3 (1,2,3) iip3 iip3 C 75 C dbm iip3 conditions, tab. 11 sv lte intermodulation (1,2,3) iip3,svlte iip3,sv C 75 C dbm sv-lte conditions, tab. 12 1) terminating port impedance: z 0 = 50
2) supply voltage: v dd = 2.3 3.6 v 3) on application board without any matching components final data sheet 9 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch rf large signal parameters table 10: iip2 conditions table band in-band frequency blocker frequency 1 blocker power 1 blocker frequency 2 blocker power 2 [mhz] [mhz] [dbm] [mhz] [dbm] band 1 low 2140 1950 20 190 -15 band 1 high 2140 1950 20 4090 -15 band 5 low 881.5 836.5 20 45 -15 band 5 high 881.5 836.5 20 1718 -15 table 11: iip3 conditions table band in-band frequency blocker frequency 1 blocker power 1 blocker frequency 2 blocker power 2 [mhz] [mhz] [dbm] [mhz] [dbm] band 1 2140 1950 20 1760 -15 band 5 881.5 836.5 20 791.5 -15 table 12: sv-lte conditions table band in-band frequency blocker frequency 1 blocker power 1 blocker frequency 2 blocker power 2 [mhz] [mhz] [dbm] [mhz] [dbm] band 5 872 827 23 872 14 band 13 747 786 23 747 14 band 20 878 833 23 2544 14 final data sheet 10 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch mipi rffe specification 6 mipi rffe specification all sequences are implemented according to the mipi alliance specification for rf front-end control interface document version 1.10 - 26. july 2011. table 13: mipi features feature supported comment register write command sequence yes register read command sequence yes extended register write command sequence no up to 4 bytes extented register read command sequence no up to 4 bytes register 0 write command sequence yes trigger function yes trigger assignment to each control register is supported programmable usid yes 3 register command sequence and extended register command sequence status register yes register for debugging reset yes by vio, power mode and rffe_status group sid yes usid_sel pin yes external pin for changing usid: 1: pin 5=sdata and pin 6=sclk ! 1100, 2: pin 5=sclk and pin 6=sdata ! 1101 full speed write yes half speed read yes full speed read yes table 14: startup behavior feature state comment power status low power the chip is in low power mode aer startup trigger function enabled trigger function is enabled aer startup. trigger function can be disabled via pm_trig register. figure 4: received clock signal constraints final data sheet 11 revision 2.0 2017-06-12 v tpma x v tnmin t sclkih t sclkil
BGSA141MN10 low resistance antenna aperture switch mipi rffe specification table 15: mipi rffe operating timing parameter symbol values unit note / test condition min. typ. max. sclk frequency fsclk 0.032 C 26 mhz full speed 0.032 C 13 mhz half speed sclk period tsclk 0.038 C 32 s full speed 0.077 C 32 s half speed sclk low period tsclkil 11.25 C C ns full speed, see fig. 4 24 C C ns half speed, see fig. 4 sclk high period tsclkih 11.25 C C ns full speed, see fig. 4 24 C C ns half speed, see fig. 4 sdata setup time ts 1 C C ns full speed, see fig. 5 2 C C ns half speed, see fig. 5 sdata hold time th 5 C C ns full speed, see fig. 5 5 C C ns half speed, see fig. 5 sdata release time tsdataz C C 10 ns full speed, see fig. 6 C C 18 ns half speed, see fig. 6 time for data output td C C 10.25 ns full speed, see fig. 7 C C 22 ns half speed, see fig. 7 sdata rise/fall time tsdataotr 2.1 C 6.5 ns full speed, see fig. 7 2.1 C 10 ns half speed, see fig. 7 vio rise time tvio-r 10 C 450 s see fig. 8 vio reset time tvio-rst 10 C C s see fig. 8 reset delay time tsigol 0.12 C C s see fig. 8 final data sheet 12 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch mipi rffe specification figure 5: bus active data receiver timing requirements figure 6: bus park cycle timing final data sheet 13 revision 2.0 2017-06-12 v tpma x v tpmin v tpma x v tpmin t s t h t h sclk sd a t a t s t sd a t az sclk sd a t a v ohmin v olma x bus p ark cy cle signal driv en signal not driv en, pull do wn only t is measur ed fr om sclk v le v el f or a de vice r eceiving sclk and driving sd a t a lines sd a t az tn v tpma x v tnmin
BGSA141MN10 low resistance antenna aperture switch mipi rffe specification figure 7: bus active data transmission timing specification figure 8: requirements for vio-initiated reset final data sheet 14 revision 2.0 2017-06-12 v ohmin v olma x v tpma x v tpmin t d sclk sd a t a t sd a t a o tr t sd a t a o tr t d t sigol time vio (v) vio ma x vio min v vio-r s t (0.2v) not t o sc ale sclk & sd a t a mus t be held a t lo w le v el fr om deassertion of vio un til the end of t sigol all sla v e r egis t er s se t/r ese t t o manuf actur er ? s de f aults t vio-r s t t vio-r
BGSA141MN10 low resistance antenna aperture switch mipi rffe specification table 16: register mapping register address register name data bits function description default broadcast_id support trigger support r/w 0x0000 register_0 7:0 mode_ctrl rf switch control 00000000 no yes r/w 0x001d product_id 7:0 product_id this is a read-only register. however, during the programming of the usid a write com- mand sequence is performed on this register, even though the write does not change its value. 00011100 no no r 0x001e manufacturer_id 7:0 manufacturer_id [7:0] this is a read-only register. however, during the programming of the usid, a write com- mand sequence is performed on this register, even though the write does not change its value. 00011010 no no r 0x001c pm_trig 7:6 pwr_mode 00: normal operation 10 yes no r/w 01: default settings (startup) 10: low power (low power) 11: reserved 5 trigger_mask_2 if this bit is set, trigger 2 is disabled. when all triggers disabled, if writing to a register that is associated to trigger 2, the data goes directly to the destination register. 0 no 4 trigger_mask_1 if this bit is set, trigger 1 is disabled. when all triggers disabled, if writing to a register that is associated to trigger 1, the data goes directly to the destination register. 0 no 3 trigger_mask_0 if this bit is set, trigger 0 is disabled. when all triggers disabled, if writing to a register that is associated to trigger 0, the data goes directly to the destination register. 0 no 2 trigger_2 a write of a one to this bit loads trigger 2s reg- isters. 0 yes 1 trigger_1 a write of a one to this bit loads trigger 1s reg- isters. 0 yes 0 trigger_0 a write of a one to this bit loads trigger 0s reg- isters. 0 yes 0x001f man_usid 7:6 spare these are read-only bits that are reserved and yield a value of 0b00 at readback. 00 no no r/w 5:4 manufacturer_id [9:8] these bits are read-only. however, during the programming of the usid, a write command sequence is performed on this register even though the write does not change its value. 01 3:0 usid programmable usid. performing a write to this register using the described program- ming sequences will program the usid in de- vices supporting this feature. these bits store the usid of the device. see tab. 13 0x001a rffe_status 7 software reset 0: normal operation 0 no no r/w 1: soware reset 6 command_frame_ parity_err command sequence received with parity er- ror - discard command. 0 no no r 5 command_length_err command length error 0 4 address_frame_ parity_err address frame parity error = 1 0 3 data_frame_ parity_err data frame with parity error 0 2 read_unused_reg read command to an invalid address 0 1 write_unused_reg write command to an invalid address 0 0 bid_gid_err read command with a broadcast_id or group_sid 0 0x001b group_sid 7:4 reserved 0000 no no r/w 3:0 group_sid group slave id 0000 final data sheet 15 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch mipi rffe specification table 17: switch mipi control combinations (truth table) register_0 C switch control register state mode d7 d6 d5 d4 d3 d2 d1 d0 0 isolation mode (open) 0 0 0 0 0 0 0 0 1 rf1 0 0 0 0 0 0 0 1 2 rf2 0 0 0 0 0 0 1 0 3 rf3 0 0 0 0 0 1 0 0 4 rf4 0 0 0 0 1 0 0 0 5 rf1||rf2 0 0 0 0 0 0 1 1 6 rf1||rf3 0 0 0 0 0 1 0 1 7 rf1||rf4 0 0 0 0 1 0 0 1 8 rf2||rf3 0 0 0 0 0 1 1 0 9 rf2||rf4 0 0 0 0 1 0 1 0 10 rf3||rf4 0 0 0 0 1 1 0 0 11 rf1||rf2||rf3 0 0 0 0 0 1 1 1 12 rf1||rf2||rf4 0 0 0 0 1 0 1 1 13 rf1||rf3||rf4 0 0 0 0 1 1 0 1 14 rf2||rf3||rf4 0 0 0 0 1 1 1 0 15 rf1||rf2||rf3||rf4 0 0 0 0 1 1 1 1 16 rfc short to gnd x 1 x x x x x x final data sheet 16 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch application information 7 application information pin configuration and function figure 9: BGSA141MN10 pin configuration - usid 1100 and usid 1101 (top view) table 18: pin definition and function usid 1100 pin no. name function 1 rf1 rf1 port 2 rf2 rf2 port 3 vdd power supply 4 vio rffe power supply 5 sdata mipi rffe data 6 sclk mipi rffe clock 7 gnd ground 8 rf3 rf3 port 9 rf4 rf port 10 rfc common rf port table 19: pin definition and function - usid 1101 pin no. name function 1 rf1 rf1 port 2 rf2 rf2 port 3 vdd power supply 4 vio rffe power supply 5 sclk mipi rffe clock 6 sdata mipi rffe data 7 gnd ground 8 rf3 rf3 port 9 rf4 rf port 10 rfc common rf port final data sheet 17 revision 2.0 2017-06-12 s s
BGSA141MN10 low resistance antenna aperture switch package information 8 package information figure 10: tsnp-10-3 package outline (top, side and bottom views) figure 11: marking specification (top view): date code digits y and w defined in table 20 / 21 final data sheet 18 revision 2.0 2017-06-12 999 99 9 9 9 99 9 9 tsnp-10-3-mk v02 pin 1 marking m5 type code date code (yw)
BGSA141MN10 low resistance antenna aperture switch package information table 20: year date code marking - digit "y" year "y" year "y" year "y" 2000 0 2010 0 2020 0 2001 1 2011 1 2021 1 2002 2 2012 2 2022 2 2003 3 2013 3 2023 3 2004 4 2014 4 2024 4 2005 5 2015 5 2025 5 2006 6 2016 6 2026 6 2007 7 2017 7 2027 7 2008 8 2018 8 2028 8 2009 9 2019 9 2029 9 table 21: week date code marking - digit "w" week "w" week "w" week "w" week "w" week "w" 1 a 12 n 23 4 34 h 45 v 2 b 13 p 24 5 35 j 46 x 3 c 14 q 25 6 36 k 47 y 4 d 15 r 26 7 37 l 48 z 5 e 16 s 27 a 38 n 49 8 6 f 17 t 28 b 39 p 50 9 7 g 18 u 29 c 40 q 51 2 8 h 19 v 30 d 41 r 52 3 9 j 20 w 31 e 42 s 10 k 21 y 32 f 43 t 11 l 22 z 33 g 44 u final data sheet 19 revision 2.0 2017-06-12
BGSA141MN10 low resistance antenna aperture switch package information figure 12: footprint recommendation figure 13: tsnp-10-3 carrier tape final data sheet 20 revision 2.0 2017-06-12 xxx x x x x x xxx
BGSA141MN10 low resistance antenna aperture switch revision history page or item subjects (major changes since previous revision) revision 2.0, 2017-06-12 release as final version final data sheet 21 revision 2.0 2017-06-12
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